(1.) Field of the Invention
The present invention relates to a method for making low-resistance contacts between polysilicon and metal silicide for multilevel interconnections on semiconductor integrated circuits. More particularly, the method relates to forming low-resistance contacts using a rapid thermal process (RTP), thereby eliminating the need to overetch the contact holes to remove the silicide between interconnecting polycide layers.
(2.) Description of the Prior Art
Continuing advances in high-resolution photolithography and anisotropic plasma etching have reduced the minimum feature sizes of semiconductor devices. For example, the current minimum feature size of the gate electrodes for field effect transistor semiconductor devices is sub-half-micromenter (.mu.m) (about 0.35 .mu.m or less). These reduced feature sizes require smaller contact holes that lead to higher contact resistance (R.sub.c). For example, current contact hole feature sizes are now typically much less than 0.5 micrometer (.mu.m), and to make contacts to the FET gate electrodes, the contacts must be less than 0.35 .mu.m in width or diameter. The increase in this parasitic resistance in series with circuit devices, such as field effect transistors (FETs), degrades the circuit performance and therefore is undesirable. A further concern is the wide distribution in contact resistance (R.sub.c) that can occur over the large number of contact holes that are simultaneously etched, and is also very undesirable.
It is common practice in the semiconductor industry to interconnect the semiconductor devices by using multilayers of patterned heavily doped polysilicon having a top silicide layer, commonly referred to as polycide layers, and by metal layers to form the integrated circuits. Because of electrical device characteristics and temperature considerations, it is desirable to form the gate electrodes for FETs and the next level of electrical interconnections contacting the gate electrodes from a first and second level of patterned polycide layers, respectively. An InterLevel Dielectric (ILD) layer, hereafter referred to as simply a dielectric layer, is used between the patterned polycide layers to electrically insulate the various levels of patterned polycide layers. Contact holes are formed in the dielectric layer to electrically interconnect the first and second polycide layers. On Ultra Large Scale Integration (ULSI), the number of contacts now well exceeds a million, and it is important to have consistently low and tight distributions of the contact resistance (R.sub.c).
The problem of high contact resistance is of particular concern between the two patterned tungsten polycide (silicide (WSi.sub.2)/polysilicon) layers used to form the gate electrodes of the pass transistors (FETS) and the word lines for the dynamic random access memory (DRAM) and other integrated circuits, such as static random access memory (SRAM), microprocessors, and the like.
Unfortunately, when the contact holes are etched in the dielectric layer to the first polycide layer, it is difficult to form consistently low contact resistance. For example, contacts having minimum feature sizes of 0.5 .mu.m or less can have contact resistance that varies from as low as 100 ohms to values exceeding 2000 ohms. Furthermore, interface treatments, such as plasma etching in a gas mixture containing CH.sub.4 and O.sub.2 to treat the tungsten silicide surface, are not effective, even when portions of the top surface of the first silicide layer are removed. Also, implant doping of the tungsten silicide layer in the contact holes does not provide consistently low contact resistance. One method of consistently reducing the contact resistance is to completely remove the first silicide layer in the contact holes. However, it would be desirable to avoid overetching the contact holes and removing completely the first silicide layer to the first polysilicon layer.
Several methods of forming polycide structures are described in the literature, but do not address the contact resistance problem. For example, Moslehi, U. S. Pat. No. 5,322,809, teaches a method for making self-aligned silicide on the source/drain and FET gate electrode of different thickness, but does not address the high-resistance contact problem between polycide levels. Kapoor, U. S. Pat. No. 5,498,558, shows a method of forming a floating electrode structure for EPROM applications, and completes the structure by forming contacts of doped polysilicon or tungsten to the source/drain and control gate electrode. However, the gate electrode is polysilicon and not polycide, and therefore would not experience the high contact resistance problem. Redwine, U. S. Pat. No. 5,109,258 teaches a method for making memory cells by selective oxidation of polysilicon, and uses a platinum silicide layer on the gate to provide low resistance, but does not address the problem of high contact resistance as commonly experienced with the refractory metals, such as tungsten. Mutsaers et al., U.S. Pat. No. 5,399,235, teach a method for making two levels of aluminum conducting tracks, and would not be concerned or address high contact resistance between polycide layers.
Therefore, there is still a need in the semiconductor industry to reduce the contact resistance between tungsten polycide layers, while avoiding the necessity of removing the first silicide in the contact holes.